A conventional complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cell 10 typically consists of six metal-oxide-semiconductor field effect transistors (MOSFETs): two P-channel field-effect transistors (PFETs) for a pull-up operation, two N-channel field-effect transistors (NFET) for a pull-down operation, and two NFETs for input/output access, i.e., pass-gate access, is shown in FIG. 1A. P1 and N1 form an inverter 12, which is cross-coupled with another inverter consisting of P2 and N2. The devices 16, 18 labeled NL and NR are pass-gate access devices which control reading from and writing into the SRAM cell 10. The corresponding layout for the circuit 10 is shown in FIG. 1B. For the sake of simplicity, metal layout shapes are not shown. In the particular layout, the word line (WL) is shown along the horizontal direction. The left bit line BL, the right bit line BR, and the ground line GND are also shown.
A conventional SRAM array consists of m rows and n columns of the aforementioned SRAM cells. Cells of the same row share one WL 20, while cells of the same column share the same bit line pair 22, 24 consisting of BL and BR. The aforementioned design is used in many SRAMS, including for example, a 1-mega-bit memory having typically 1024 by 1024 cells.
During standby, all the WLs are at low (i.e., at GND level) and all the bit lines are biased to the standby voltage level (of the power supply) Vdd. Thus, the NFET pass-gate devices NL and NR of all the cells are shut off. A data bit 1 is maintained with P1 and N2 on, and P2 and N1 off, such that the left cell node CL is high (i.e. at Vdd) while CR is low (GND). Correspondingly, a data bit 0 is maintained when P2 and N1 are on, and P1 and N2 are off, which forces the right cell node CR to high (i.e., Vdd) and the left cell node CL to GND. During access time, one WL is selected by being switched on (to Vdd) such that half of the PFET pass-gate devices along the selected WL are turned on simultaneously. For each cell along the selected WL, one pass-gate device is turned on.
During a read access operation, either BL or BR are pulled down from their high (at Vdd) by the cell. BL is pulled down if the cell is at 0, whereas BR is pulled down if the cell is at 1. A bit select multiplexor then steers the selected bit pair(s) to appropriate sense amplifiers to generate the digital signals for external circuitry requesting the read memory operation. The sense signals developed along the unselected bit columns are ignored. The cells along the selected WL that were not selected are referred to as the “half-selected” cells.
During a write access operation, the bit select circuitry steers the input data into the selected bit pairs. To write a 1, BL is driven to high (i.e., Vdd) and BR to low (i.e., to GND), shutting off N1 and P2, while turning on N2 and P1. To write a 0, BL is forced to low and BR to high. Along the unselected bit columns, BL and BR are coupled to VDD and are gradually pulled down by the “half-selected” cells, as previously described in the read operation. Thus, during a read access operation, all the cells along the selected WL are disturbed since one NFET pass-gate device of each SRAM cell remains on. During a write access, all the “half-selected” cells are similarly disturbed as during the read operation. When a cell is at 0, the left cell node CL is at GND. When WL is raised to high (i.e., Vdd), the pass-gate device NL switches on, raising BL to VDD and pulling the left cell node up. Thus, NL and N1 act as a potential divider at the left cell node CL between Vdd and GND. To prevent the left cell node CL from rising beyond the threshold voltage of N2, the conductance of N1 must be larger than the conductance of NL. Otherwise, N2 turns on, pulling down the node CR, switching P1 on, and raising the node CL from GND to Vdd. In such an instance, the cell is disturbed from its 0 state to a 1 state.
Thus, the ratio of the conductance of N1 over the conductance of NL is a basic metric to measure the stability of the SRAM cell or the ability of the cell to retain its data state. This ratio is referred to by CMOS SRAM designers as “beta” or “beta ratio”. It is defined as the ratio of the conductance of the pull-down device over the conductance of pass-gate device. The larger the beta ratio, the cell becomes more stable, and its static noise margin (SNM) increases.
The conductance of a transistor is approximately proportional to the effective carrier mobility μeff and to the ratio of the device width to the channel length (W/L). The beta of the SRAM cell can be approximated by the ratio of of μeff (W/L) of transistor N1 and μeff (W/L) of transistor NL. If N1 and NL have the same channel length, then the beta ratio becomes the ratio of the channel width of N1 over the channel width of NL. Depending on the SRAM application, beta ranges from 1.8 to 3.
It is known that writability is the obverse of stability. The more stable the cell the more difficult it will be to write the cell into a different state. As indicated above, a cell design with a narrower pass-gate device will be more stable, but as the current through such a device is smaller. It will require more time to develop a signal of a given magnitude on the bit line. The rate at which the cell can pull down a bit line is limited by the series combination of the pull-down device and the pass-gate device, and is increased by increasing the conductance of either or both devices. For minimum read delay, the widths of both devices should therefore be as wide as possible. In practice, the cell size and the desired beta ratio limit the size of the devices.
The reduction in the size of MOSFETs has provided continued improvement in speed performance, size, and density of SRAM chips. However, as the gate length of the conventional bulk MOSFET is reduced, it suffers from problems related to the inability of the gate to substantially control the on and off states of the channel. Phenomena such as reduced gate control associated with the transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects. FIGS. 2A and 2B show the cross-sectional views of conventional MOSFETs 30, 40 formed on bulk silicon substrate 26 and on silicon-on-insulator substrate 28. The MOSFETs of FIGS. 2A and 2B are used to configure the SRAM cell 10 shown in FIGS. 1A and 1B.
For device scaling well into the sub-30-nm regime, the requirements for body-doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles become increasingly difficult to meet when conventional device structures based on bulk silicon (Si) substrates are employed. For device scaling well into the Sub-30-nm regime, a promising approach for controlling short-channel effects is to use an alternative device structure with multiple-gates. Examples of multiple-gate transistor structures include the double-gate transistor structure, triple-gate transistor structure, and the omega-FET structure. A multiple-gate field-effect transistor (MGFET) structure is expected to extend the scalability of CMOS technology beyond the limitations of the conventional bulk MOSFET and realize the ultimate limit of silicon MOSFETs. The introduction of additional gates improves the capacitance coupling between the gates and the channel, increases the control of the channel potential by the gate, helps suppress short channel effects, and prolongs the scalability of the MOS transistor.
While there is some work on the design and fabrication of multi-gate devices such as the double-gate and triple-gate devices, there is little work on circuits, such as inverter circuits and static random-access memory (SRAM) cells, configured using such devices. The relentless pursuit of high performance has pushed logic and circuit designers to utilize every delay and area optimization technique at their disposal. However, the optimization of circuits, such as SRAM cells, incorporating multiple-gate transistors has not been addressed. Since the performance of CMOS SRAM circuits depend significantly on the beta ratio, it is crucial to make avail a simple method to provide optimal P/N width ratios for inverters incorporating multiple-gate transistors. Moreover, the use of multiple-gate transistors may result in significant savings in the layout area in the case where small device width transistors in the conventional SRAM cell are replaced with multiple-gate transistors comprised of tall fins. This is especially true when the number of fins constituting each multiple-gate transistor is small, for example, less than or equal to three.
It is therefore an object of the present invention to provide a SRAM cell comprising multiple-gate field-effect transistors (MGFETs).
It is another object of the present invention to provide a SRAM cell with an adjustable beta ratio between the pull-down and pass-gate multiple-gate devices.
It is a further object of the present invention to provide savings in layout area of the SRAM cell.
It is yet another object of the present invention to provide an array of SRAM cells configured using multiple-gate field-effect transistors.